Device guidance

LM74930-Q1 is the selected input-protection controller ahead of the LM61440-Q1 buck regulator in Hengshun's calculated 12 V nominal automotive reference design. It supervises external common-source pass MOSFETs, UV/OV thresholds, inrush slew, current limit and fault timing to create VPROTECTED. It is not the buck regulator, and its controller functions do not by themselves establish load-dump survival, reverse-battery performance, MOSFET safe operating area, TVS energy margin or system compliance.

Thermal considerations

  • Separate steady-state conduction checks from transient linear-mode stress; low static on-resistance does not establish hot pulse SOA.
  • Measure pass-FET, shunt, TVS and controller temperatures under jump-start, reverse-battery, inrush, overcurrent and selected transient profiles.

Protection considerations

  • The selected architecture uses LM74930QRGERQ1 with two BUK7J2R4-80M MOSFETs, a bidirectional 3.0SMCJ30CAQ-13 TVS and a 2 mΞ© WSL2512R0020FEA shunt.
  • The calculated nominal current-limit target is 4.502 A, with exact tolerance, blanking, parasitic and short-circuit peak behavior reserved for simulation and bench work.
  • A static threshold or rating comparison cannot be restated as proof of dynamic protected-node overshoot, load-dump survival, TVS energy, pass-FET SOA or reverse-polarity performance.

Application contexts

  • Between the vehicle battery interface and a downstream converter that requires a bounded protected-node envelope
  • Automotive ECU front ends that need coordinated reverse blocking, disconnect, surge planning, inrush control and current sensing

Typical architectures

  • Connector-side bidirectional TVS followed by two common-source N-channel pass MOSFETs, Kelvin current shunt and protected-node filtering interface
  • Controller-supervised clamp/disconnect stage feeding local buck input capacitance and the primary regulator

Electrical considerations

  • Translate cold-crank, normal, jump-start, reverse-battery and transient requirements into UV/OV thresholds, device ratings, timers and validation waveforms.
  • Check external MOSFET voltage rating, hot on-resistance, gate stress, linear-mode SOA and thermal trajectory for every clamp and disconnect event.
  • Coordinate the TVS standoff and clamp behavior with source impedance, pulse energy, controller timing, wiring inductance and the protected-node ceiling.

Input and output design

  • The current calculated front end targets 9–18 V normal input, 4.5 V cold-crank ride-through once enabled, 27 V / 60 s jump start and βˆ’14 V / 60 s reverse blocking.
  • Its static UV rising range is 4.289–4.824 V and falling range is 3.906–4.389 V; the static OV rising range is 29.821–33.442 V and falling range is 27.169–30.418 V.

Capacitor selection

  • The current 4.7 nF dV/dt capacitor is only an inrush starting point calculated from the nominal 18.8 Β΅F downstream bank and a 0.22 A target.
  • Recalculate slew and inrush with final effective downstream capacitance, any added EMI/filter capacitance, cable impedance and the real startup sequence.

Layout considerations

  • Place the TVS at the connector with a short high-current return and keep its pulse path out of quiet controller ground and threshold networks.
  • Use Kelvin traces for the current shunt, compact gate loops and gate resistors at the MOSFETs; reserve the defined post-shunt filtering and damping interface for evidence-led tuning.

Suitable applications

  • 12 V nominal automotive ECU input protection ahead of a defined downstream power stage
  • Protected-node architectures that need an external-MOSFET controller and an explicit transient-validation plan
Official manufacturer product documentation β†—Official datasheet β†—

01

Selected role ahead of the buck stage

The current Hengshun reference design places LM74930QRGERQ1 between the battery connector and the LM61440-Q1 converter. A connector-side bidirectional TVS and two common-source N-channel MOSFETs form the high-current path, followed by a Kelvin-sensed shunt and VPROTECTED. The controller supervises that path; the downstream LM61440-Q1 performs the 5 V buck conversion.

Controller
LM74930QRGERQ1
Pass devices
2 Γ— BUK7J2R4-80M, common-source
Clamp device
3.0SMCJ30CAQ-13, bidirectional TVS
Current shunt
WSL2512R0020FEA, 2 mΞ©

02

Protected-node planning

VPROTECTED is a design boundary rather than a guarantee created by a single controller. The present calculation intends 6–28 V continuous operation for the downstream buck and a protected event target no higher than 36 V. The maximum calculated OV rising threshold is 33.442 V, but wiring inductance, TVS behavior, controller response and MOSFET turn-off can create dynamic overshoot. That waveform must be simulated and captured before the boundary can be treated as evidence.

03

UV, OV, inrush and current-sense choices

For the current design, the UV divider calculates 4.289–4.824 V rising and 3.906–4.389 V falling; the OV divider calculates 29.821–33.442 V rising and 27.169–30.418 V falling. A 2 mΞ© shunt with 49.9 Ξ© RSET and 66.5 kΞ© RILIM gives the 4.502 A nominal current-limit target. A 4.7 nF dV/dt capacitor and 68 nF timer capacitor are starting values whose tolerances and real waveforms remain review items.

04

Pass MOSFET and TVS coordination

The two selected 80 V BUK7J2R4-80M MOSFETs provide reverse blocking and controlled disconnect in the calculated topology. The 30 V standoff bidirectional TVS is positioned at the connector so reverse battery does not create the forward-conduction conflict of a unidirectional clamp. Static voltage headroom is positive in the locked comparison, but load-dump source impedance, pulse duration, repetition, hot TVS behavior and the MOSFET linear-mode trajectory determine whether the physical design survives.

05

High-current layout and filtering interface

Keep the TVS pulse loop short and physically separate from threshold-divider and controller references. Route both shunt-sense conductors as a Kelvin pair, constrain the MOSFET gate loops and place damping resistors at the gates. The existing design reserves a post-shunt Ο€-filter or damped-LC interface; component values must be chosen from source/load impedance and emissions evidence rather than populated by assumption.

06

Dynamic evidence required

Release work must capture battery input, VPROTECTED, MOSFET VDS and VGS, TVS current, timer behavior, inrush and fault currents under defined tests. It must also compare the hot pulse trajectory with derated MOSFET SOA, integrate TVS energy, verify βˆ’14 V / 60 s reverse behavior and run thermal and EMI evaluations on the actual assembly. No such bench, dynamic transient, SOA, TVS-energy, reverse-polarity or compliance evidence is completed in the current record.