Hengshun Power
Reference Designs
Use reviewed reference designs to connect a defined input and output requirement with topology, selected components, calculations, layout priorities and the evidence still needed before production use. Published records now cover protected BMS auxiliary power, calculated 36–60 V wide-input conversion, a calculated 12 V to 5 V / 3 A automotive buck, and an English-only calculated ADAS camera 12 V to 5 V to 3.3 V power architecture with explicit validation limits.
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12 reviewed entries
12V to 5V / 3A Automotive Buck Converter
Calculated reference designCalculated automotive power reference design for a protected 6–28 V input and a 5 V / 3 A output using LM61440-Q1. It publishes the locked power-stage and front-end calculations while keeping capacitor derating, transient dynamics, thermal, EMI and bench evidence explicitly open.
Review calculated design ↗24V to 5V / 3A Industrial Wide-Input Buck
Calculated reference designCalculated engineering publication candidate for a protected 24 V industrial input and a 5 V / 3 A output using LM76003RNPT. It records the locked input boundary, power-stage calculations, explicit BOM maturity and an unexecuted validation plan without making a board, surge, thermal, EMI or compliance claim.
Review calculated design ↗36–60 V to 12 V / 1 A Wide-Input DC-DC Reference Design
Calculated reference designCalculated synchronous buck reference design for a 36–60 V continuous input and a 12 V / 1 A output using LMR38020-Q1. It publishes the power-stage calculations and BOM maturity while keeping front-end protection explicitly provisional.
Review calculated design ↗12 V Automotive Always-On 3.3 V / 300 mA Ultra-Low-IQ Buck Reference Design
Calculated reference designCalculated LM5164-Q1 always-on automotive buck reference design for a protected 6–36 V node and a 3.3 V / 300 mA keep-alive rail, with device-IQ context, explicit calculation provenance and fifteen planned, unexecuted validation items.
Review calculated design ↗48 V Zonal Controller Dual-Domain Power Architecture
Calculated reference designApplication-first architecture for a protected 48 V vehicle backbone that keeps local 48 V loads, retained 12 V legacy loads and low-voltage auxiliary rails under explicit protection, fault and power-state ownership.
Review calculated design ↗12/24V to 5V BMS Auxiliary Power Reference Design
Calculated reference designCalculated reference design for a protected 7–36 V input synchronous buck stage using LM5161-Q1 to produce a 5 V / 1 A BMS auxiliary rail. It separates raw battery events from protected VIN, shows the selected values and margins, and identifies the simulation, prototype and compliance evidence that is still required.
Review calculated design ↗ADAS Camera Power Architecture — 12V to 5V to 3.3V
Calculated reference designCalculated reference design for a protected 12 V automotive source feeding a 5 V / 0.65 A LM65625-Q1 buck stage and a 3.3 V / 0.40 A LM1117-Q1 rail. The architecture, calculations and BOM maturity are documented; board, thermal, EMI, noise, PSRR and camera-module validation have not been executed.
Review calculated design ↗20–60 V to Isolated 15 W Industrial Auxiliary Flyback Reference Design
Calculated reference designCalculated primary-side-regulated isolated flyback publication candidate for a protected 20–60 V industrial source and a 16.4 V / 0.9 A / 14.76 W auxiliary output using LM5185QPWPRQ1. It preserves the official 20–60 V, 16.4 V / 1 A TI EVM as reference evidence while keeping the Hengshun target, BOM maturity and thirteen unexecuted validation gates explicit.
Review calculated design ↗24 V Input to +15 V / -5 V Isolated SiC Gate-Driver Bias Supply
Calculated reference designCalculated UCC14240-Q1 isolated gate-driver bias publication candidate for a protected 24 V auxiliary rail. It converts the official 21–27 V normal input range into +15 V and -5 V rails for a calculated 1.25 W load while keeping the project-defined 30 V protected-node event, basic-isolation boundary, provisional passives and unexecuted validation work explicit.
Review calculated design ↗12 V to 0.8 V / 70 A Two-Phase High-Current Point-of-Load Power Module
Calculated reference designCalculated TPSM8D6C24 high-current point-of-load publication candidate for industrial FPGA and ASIC compute. One two-phase module converts a protected 5–16 V intermediate bus to a 0.8 V / 70 A design target while keeping thermal derating, copper and interconnect design, capacitor selection, PMBus configuration and all physical validation explicitly open.
Review calculated design ↗6–18 V to 24 V / 2 A Automotive Boost Converter
Calculated reference designCalculated LM5155-Q1 non-synchronous boost reference design for a protected 6–18 V automotive input and 24 V / 2 A output, with explicit component maturity and unexecuted validation boundaries.
Review calculated design ↗5–20 V Input to 2S Li-Ion / 3 A Buck-Boost Charger with NVDC Power Path
Calculated reference designCalculated BQ25798 four-switch buck-boost charger reference design for a 5–20 V source, a 2S Li-ion pack and an NVDC system rail, with source-limited low-line behavior and explicit evidence boundaries.
Review calculated design ↗Start with the requirement
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Describe the application, input range, output rails and the issue you need to resolve. Project scope and deliverables are agreed separately.