01

Key design targets

This calculated publication candidate converts a nominal 12 V automotive source into a 5 V / 3 A rail. Normal battery operation is 9–18 V, while the protected converter node is designed for 6–28 V continuous operation. Cold crank may fall to 4.5 V with reduced or dropout output below 6 V and controlled restart; jump start targets full regulation at 27 V for 60 seconds, and reverse input targets front-end blocking without damage at −14 V for 60 seconds ± 6 seconds.

Conversion
Protected synchronous buck
Output
5 V / 3 A / 15 W
Cold crank
4.5 V; dropout allowed below 6 V
Jump start
27 V / 60 s regulation target
Reverse input
−14 V / 60 s ± 6 s no-damage target
Protected node
≤36 V clamp-and-disconnect target

02

Validation status and claim limits

The design has passed calculated publication-candidate review with bounded validation limitations. Calculations and selected identities are public engineering evidence, but no simulation, prototype measurement, thermal result, EMI result, compliance test or production release is implied. These limitations apply before interpreting the front-end or power-stage targets.

Evidence still open

  • No bench validation and no measured line, load, ripple, startup or fault evidence.
  • No validated thermal margin, EMI performance or automotive compliance claim.
  • No validated load-dump survival, dynamic clamp overshoot, TVS energy or external-MOSFET SOA.
  • No validated reverse-battery event, inrush behavior or repeated-fault recovery.
  • CIN effective capacitance at 28 V is unresolved; CGA8N3X7S2A475K230KB is Production NRND.
  • No schematic, layout or bill of materials is approved for production use.

03

Architecture overview

An LM74930QRGERQ1 front-end controller drives two BUK7J2R4-80M back-to-back MOSFETs and coordinates the 3.0SMCJ30CAQ-13 bidirectional TVS, 2 mΩ WSL2512R0020FEA current shunt, UV/OV thresholds, current limit, fault timers and controlled inrush. The protected node feeds LM61440AASQRJRRQ1, a synchronous buck in the 14-pin VQFN-HR RJR package configured for 400 kHz Auto mode with spread spectrum enabled. This separation keeps raw battery protection evidence distinct from buck-regulation evidence.

Front-end controller
LM74930QRGERQ1
Pass MOSFETs
2 × BUK7J2R4-80M
TVS
3.0SMCJ30CAQ-13 · bidirectional
Current shunt
WSL2512R0020FEA · 2 mΩ
Buck regulator
LM61440AASQRJRRQ1
Inductor
XAL1080-103MED · 10 µH

04

Power-stage calculations

The locked analytical model uses 400 kHz, a 10 µH nominal inductor and an 8 µH minimum inductance case. Timing margins remain positive at the four calculated input points. The worst minimum-inductance peak is 3.641741 A, leaving +0.358259 A against a conservative 4 A limit; this margin is positive but tight and unvalidated. The calculated inductor RMS current is 3.022793 A, and the 100 kΩ / 24.9 kΩ divider targets 5.016064 V.

Locked HGS15F buck operating points at 400 kHz and 10 µH nominal
VINDutyTonToffRipplePeakValleyTon marginToff margin
6 V0.8333332083.333 ns416.667 ns0.208333 A3.104167 A2.895833 A2013.333 ns331.667 ns
12 V0.4166671041.667 ns1458.333 ns0.729167 A3.364583 A2.635417 A971.667 ns1373.333 ns
18 V0.277778694.444 ns1805.556 ns0.902778 A3.451389 A2.548611 A624.444 ns1720.556 ns
28 V0.178571446.429 ns2053.571 ns1.026786 A3.513393 A2.486607 A376.429 ns1968.571 ns

05

Front-end protection

Static calculations place UV rising at 4.289–4.824 V and falling at 3.906–4.389 V using 100 kΩ / 15.4 kΩ. The 100 kΩ / 1.96 kΩ OV divider places rising at 29.821–33.442 V and falling at 27.169–30.418 V. RSET is 49.9 Ω, RILIM is 66.5 kΩ for a 4.502 A nominal current-limit target, CTMR is 68 nF for 0.771–1.465 ms overcurrent and 11.333–21.156 ms OV-clamp timing, and 4.7 nF CdVdt targets 0.22 A nominal inrush from 18.8 µF nominal CIN. Dynamic overshoot, source impedance, TVS energy, MOSFET SOA and reverse behavior still require bench evidence.

06

Critical BOM

The table identifies the calculation-backed implementation baseline. Selected means the exact identity supports the present calculated design; it does not qualify the complete assembly for production. The CIN row is deliberately provisional because its 28 V effective capacitance is unresolved and the exact TDK part is Production NRND.

HGS15F / HGS15G critical publication-candidate BOM
FunctionManufacturer part or valueEngineering basisPublic status
Buck regulatorLM61440AASQRJRRQ1 · RJR-14400 kHz · Auto · soft startSelected
InductorXAL1080-103MED · 10 µHAEC-Q200; 8 µH minimum calculationSelected
Input bank4 × CGA8N3X7S2A475K230KB · 4.7 µF / 100 VAEC-Q200; exact-part model exists but numeric extraction and 28 V effective C remain unresolved; Production NRNDProvisional
Output bank4 × CGA6P1X7R1C226M250AC · 22 µF / 16 VBias and thermal validation openSelected calculated
BootstrapCGA3E2X7R1H104K080AA · 100 nFLocked exact identitySelected
Feedback100 kΩ / 24.9 kΩ5.016064 V calculatedSelected calculated
Frequency set33.2 kΩ400 kHz targetSelected calculated
Front-end controllerLM74930QRGERQ1Static threshold network calculatedSelected calculated
Pass MOSFETs2 × BUK7J2R4-80MBack-to-back; SOA and dynamics openSelected calculated
TVS3.0SMCJ30CAQ-13Bidirectional; energy and clamp dynamics openSelected calculated
Current shuntWSL2512R0020FEA · 2 mΩ4.502 A nominal current-limit targetSelected calculated
UV / OV dividers100 kΩ / 15.4 kΩ; 100 kΩ / 1.96 kΩTolerance bands calculatedSelected calculated
Timers / inrushCTMR 68 nF; CdVdt 4.7 nFTiming and nominal inrush calculatedSelected calculated

07

Official sources

Primary manufacturer pages establish device identity and provide the documentation used for the calculated candidate. Always verify document revision, ordering status and application conditions before using this record in a project; these links do not replace a project-specific design review.

Texas Instruments — LM61440-Q1Selected synchronous-buck regulator family.Coilcraft — XAL1080Selected XAL1080-103MED inductor family.Texas Instruments — LM74930-Q1Front-end ideal-diode, surge-stopper and reverse-protection controller.Nexperia — BUK7J2R4-80MSelected back-to-back pass MOSFET.Diodes Incorporated — 3.0SMCJ30CAQSelected bidirectional TVS family.Vishay — WSL2512Selected 2 mΩ current-shunt family.TDK — CGA8N3X7S2A475K230KBProvisional 100 V CIN; Production NRND and effective capacitance unresolved.

08

Bench-validation plan

A staged validation plan has been defined. No bench execution has yet been completed. The next release gate requires measured evidence on the intended PCB, harness, source impedance, load and enclosure, with setup, waveform, component revision, temperature and acceptance criteria recorded for every result.

  • PLANNED / NOT EXECUTED — Bring-up, startup, shutdown, soft start, pre-bias and controlled restart after UV events.
  • PLANNED / NOT EXECUTED — Static 5 V regulation, ripple and efficiency map at 6, 9, 12, 18 and 28 V across load.
  • PLANNED / NOT EXECUTED — 3 A operation, load-step response, current-limit margin, short circuit and repeated-retry heating.
  • PLANNED / NOT EXECUTED — Behavior below 6 V through the 4.5 V cold-crank point and recovery.
  • PLANNED / NOT EXECUTED — 27 V / 60 s jump-start regulation and component stress.
  • PLANNED / NOT EXECUTED — −14 V / 60 s ± 6 s reverse-polarity blocking and post-event recovery.
  • PLANNED / NOT EXECUTED — OV cutoff and protected-node disconnect delay, clamp level and dynamic overshoot.
  • PLANNED / NOT EXECUTED — Locked load-dump waveform, TVS pulse energy and both pass-MOSFET SOA margins.
  • PLANNED / NOT EXECUTED — Inrush and hot-plug behavior across source impedance and CIN tolerance.
  • PLANNED / NOT EXECUTED — Thermal performance on the intended PCB and enclosure across ambient and airflow limits.
  • PLANNED / NOT EXECUTED — Conducted and radiated EMI pre-compliance before any authorized standard-specific program.