ADAS Camera Power Architecture — 12V to 5V to 3.3V

01

Design intent and scope

This calculated reference design defines a generic local power tree for an automotive ADAS camera or sensing module. It converts a protected 12 V vehicle source to an intermediate 5 V rail and then to a 3.3 V rail with low-noise design intent. It is an engineering baseline, not a production schematic, released product or claim about every camera module.

02

Validation status and limitations

Official manufacturer evidence supports the selected regulator and protection identities, while the locked engineering package provides the calculations. This English publication candidate remains a calculated design. Board-level, thermal, EMI, compliance, camera integration, sequencing, noise and PSRR validation have not been executed.

Design status

Calculated design

BOM maturity

8 selected · 15 provisional · 1 deferred

Bench execution

Not executed

Production readiness

No

03

Validation limitations

No schematic, layout, prototype, waveform, efficiency result, noise result, PSRR curve, temperature result, transient-survival result, EMI result or compliance report has been approved for this design. Static calculations do not close dynamic protected-node overshoot, TVS energy, MOSFET SOA, inrush, sequence or camera-load behavior.

04

System power-tree overview

Battery-side source → LM74930-Q1 protected-input stage → LM65625-Q1 fixed 5 V / 0.65 A buck → up to 0.10 A direct 5 V load plus LM1117-Q1 fixed 3.3 V / 0.40 A LDO. The useful continuous output target is 1.82 W; the stage-1 sizing capacity is 3.25 W.

05

Battery-side and protected-input boundary

The battery-side profile carries cold crank, jump start, reverse polarity and raw vehicle disturbances. The downstream converter is designed around a separate protected-input domain of 6–28 V continuous and a ≤36 V protected-node event target. Protection hardware must prevent battery-side events from being misrepresented as regulator operating conditions.

06

Locked input profile

The reused HGS15 generic profile is 12 V nominal and 9–18 V normal continuous. Cold crank is represented by a 4.5 V, 10 s class event with reduced output allowed; jump start is 27 V for 60 s with full regulation required; reverse polarity is −14 V for 60 s ± 6 s with front-end blocking.

Protected continuous

6–28 V

Protected event target

≤36 V

Cold crank

4.5 V representative 10 s class

Jump start

27 V / 60 s

Reverse polarity

−14 V / 60 s ± 6 s

07

5 V rail requirement

The intermediate rail targets 5 V, 0.65 A and 3.25 W. The unmargined demand is 0.50011 A: up to 0.10 A direct load, 0.40 A delivered through the LDO and 0.000110 A maximum LDO quiescent current. The 0.65 A design contract provides 29.971% sizing margin.

08

3.3 V rail requirement

The second rail targets 3.3 V, 0.40 A and 1.32 W for a generic system/interface load. It has low-noise design intent; design-point noise and PSRR remain unmeasured. The 0.40 A value is also the bounded transient supply contract because no larger official startup peak was acquired.

09

Front-end protection architecture

LM74930QRGERQ1 drives two BUK7J2R4-80M common-source MOSFETs and coordinates the 3.0SMCJ30CAQ-13 bidirectional TVS, WSL2512R0020FEA 2 mΩ current shunt, UV/OV thresholds, current limit, timer and controlled inrush. The calculated reuse does not establish dynamic transient survival.

10

LM65625-Q1 first-stage selection

LM65625SRZTRQ1 is selected because its 3–65 V recommended input range gives more headroom at the 36 V protected-node event target than the allowed LM61440-Q1 alternative. Its 2.5 A rating exceeds the 0.65 A target, and the fixed 5 V, 400 kHz configuration is supported by official documentation.

11

5 V buck calculations

At 400 kHz with 10 µH nominal, ideal duty spans 0.833333 at 6 V to 0.178571 at 28 V. Worst screened ripple is 1.426091 A peak-to-peak at 28 V, 8 µH and 360 kHz; peak inductor current is 1.363046 A, leaving a calculated 2.386954 A margin to the 3.75 A minimum high-side limit. With 50 µF effective output capacitance, calculated ripple is 9.904 mV peak-to-peak before parasitics and transient effects.

12

LM1117-Q1 second-stage selection

LM111733QKVURQ1 is the only shortlisted automotive candidate that meets the 0.40 A target. The fixed 3.3 V TO-252 identity has a 1 A rating and a 67.2°C/W official junction-to-ambient metric; the two 300 mA alternatives fail the locked load gate.

13

3.3 V LDO electrical and thermal calculation

The conservative dropout calculation is 0.68 V at 0.40 A, leaving 1.02 V from a 5 V input. Calculated dissipation is 0.68055 W, and the first-order rise is 45.73296°C using 67.2°C/W. The resulting 104.26704°C mathematical ceiling is bounded to a ≤100°C screening condition only; PCB copper, airflow, enclosure and adjacent heat still require measurement, and no production ambient guarantee is established.

14

Power-tree budget

Useful output is 0.50 W on the direct 5 V load plus 1.32 W on the 3.3 V load, totaling 1.82 W. The first-stage unmargined output is 2.50055 W including the LDO input current and maximum quiescent current; the 3.25 W first-stage target includes the locked sizing margin.

15

Startup, inrush and sequencing limitations

The cascade inherently establishes the 5 V rail before the 3.3 V LDO output, but it does not define a camera-specific delay. The 4.7 nF dV/dt capacitor remains a starting value tied to 18.8 µF nominal downstream input capacitance. Load startup waveform, total effective capacitance, inrush and sequence timing must be captured on hardware.

16

Critical BOM

All 24 critical rows are shown so provisional and deferred work cannot disappear behind the selected devices. The HGS30 convergence review retained the HGS29 maturity: 8 selected, 15 provisional and 1 deferred; no row was promoted without exact official evidence.

17

Layout, grounding and EMI considerations

Place the front-end TVS, current path and MOSFET loop for minimum surge-loop inductance. Place LM65625-Q1 local bypass, power loop and bootstrap components tightly; keep switch-node copper bounded; route feedback and analog returns away from high-di/dt paths; use Kelvin sense routing at the 2 mΩ shunt. Final filtering and damping depend on measured source impedance and pre-compliance results.

18

Noise and PSRR considerations

LM1117-Q1 has vendor-characterized noise and PSRR evidence at conditions different from this design point. This design therefore describes a 3.3 V regulated rail with low-noise design intent; design-point output noise, ripple coupling and PSRR remain unmeasured. Probe technique, source ripple injection and frequency sweep must be defined before bench execution.

19

Thermal considerations

The LDO's 0.68055 W dissipation is the dominant locked thermal screen. The ≤100°C statement is conditional and calculated, not a claim that hardware works or is safe at that ambient. Measure the regulator, buck IC, inductor, pass MOSFETs, TVS, shunt and capacitors on the intended PCB across line and cross-load conditions.

20

Official evidence

The calculated design traces exact values to the locked engineering calculations and official source files. These links identify the governing manufacturer documents; they do not replace revision control, the local evidence hashes or project-specific validation.

21

Planned bench validation

The HGS30 plan defines safety inspection, equipment, board records, the full 6/9/12/18/27/28 V steady-state matrix, 5 V and 3.3 V load sweeps, cross-loads, startup, sequencing, load steps, dropout, thermal, noise, PSRR, switching ripple, EMI pre-compliance, reverse polarity, jump start, protected-node transients, SOA/energy and fault tests. It is a plan only; no physical test was executed.

• PLANNED / NOT EXECUTED — Pre-power inspection and board records
• PLANNED / NOT EXECUTED — Protected-input steady-state matrix
• PLANNED / NOT EXECUTED — 5 V regulation and load sweep
• PLANNED / NOT EXECUTED — 3.3 V regulation and load sweep
• PLANNED / NOT EXECUTED — Cross-load operation
• PLANNED / NOT EXECUTED — Startup, shutdown and inrush
• PLANNED / NOT EXECUTED — Rail sequencing
• PLANNED / NOT EXECUTED — Load-transient response
• PLANNED / NOT EXECUTED — Brownout and recovery
• PLANNED / NOT EXECUTED — Thermal characterization
• PLANNED / NOT EXECUTED — Noise and PSRR
• PLANNED / NOT EXECUTED — Switching ripple
• PLANNED / NOT EXECUTED — EMI pre-compliance
• PLANNED / NOT EXECUTED — Reverse polarity
• PLANNED / NOT EXECUTED — Jump start
• PLANNED / NOT EXECUTED — Load-dump and protected-node transients
• PLANNED / NOT EXECUTED — MOSFET SOA and TVS energy
• PLANNED / NOT EXECUTED — Short-circuit and fault behavior

22

Related public engineering context

The public LM65625-Q1 and LM74930-Q1 component guides, automotive input-transient guide and Request a Design workflow provide context for requirement discussion. This publication candidate is available only in English; no translated body or localized fallback is authorized.