36–60 V to 12 V / 1 A Wide-Input DC-DC Reference Design

01

Design at a glance

This publication candidate is a calculation-backed, non-isolated synchronous buck stage for a nominal 48 V source. It regulates across the locked 36–60 V continuous envelope and targets a 12 V / 1 A rail, while clearly separating calculated power-stage decisions from open protection and validation work.

Architecture

Non-isolated synchronous buck

Control mode

FPWM

BOM maturity

3 selected · 12 provisional

Evidence maturity

Calculated; not bench validated

Front end

Provisional; dynamic closure open

Public languages

English only

02

Design intent

The design turns a defined wide-input requirement into a reviewable power-stage calculation and a maturity-controlled BOM. It is intended to help engineers assess a 48 V vehicle subsystem, zone controller or PDU auxiliary rail, or an industrial bus conversion before committing to schematic, layout, prototype and validation work.

03

What this design does not prove

Publication makes the assumptions and calculated decisions reviewable; it does not convert open protection, component-characterization or laboratory work into validated evidence. The following boundaries are mandatory and must remain visible before the provisional front-end architecture.

04

Where this design fits

Use this calculated design when a unidirectional 36–60 V source must feed a local 12 V / 1 A rail and galvanic isolation is not required. Relevant contexts include automotive 48 V subsystems, zone controllers and power-distribution units, and industrial equipment whose continuous source and fault boundaries match the stated assumptions.

05

Power architecture

The architecture places a provisional TPS48110-Q1 controlled protection stage ahead of the LMR38020-Q1 synchronous buck. Back-to-back external MOSFETs provide a controllable path, the sense resistor defines nominal current thresholds, and the local capacitor bank supplies switching current. Protection and conversion remain separate evidence domains.

06

Continuous-input boundary

The locked calculation envelope is 36–60 V continuous input with a nominal 48 V source. The LMR38020-Q1 downstream input has an 80 V absolute limit, so residual clamp voltage, turn-off delay and parasitic overshoot must be demonstrated under a locked source event before any transient-survival statement can be made.

07

Why LMR38020-Q1

LMR38020-Q1 is the primary regulator because the selected FPWM variant supports the calculated wide-input buck stage, the 12 V / 1 A target and a 400 kHz design point. LMR38020FSQDDARQ1 is the orderable identity used for this BOM. LM5161-Q1 and LM5012-Q1 remain context alternatives, not co-primary devices.

08

Calculated operating points

The operating-point table is reproduced from the locked HGS14C R2 calculation bundle. Values are analytical, use the selected 33 µH inductance and include the calculation bundle's minimum-switching-frequency ripple case; none of the entries represents an oscilloscope or bench measurement.

09

Switching margins

The selected frequency is 400 kHz with a calculated 64.9 kΩ RT target. The locked bundle calculates a worst-case input before minimum-on-time foldback of 190.8397 V and an input before minimum-off-time foldback of 14.0187 V. These timing calculations do not establish protection capability outside the 36–60 V envelope.

10

Inductor selection

The selected XAL8080-333MED provides 33 µH with a 3.8 A minimum saturation-current requirement in the design calculation and a 1.5 A minimum RMS design target. The maximum calculated peak current at minimum switching frequency is 1.4545 A; thermal rise, core loss and saturation still require project-specific validation.

11

Capacitor strategy

The revised local input bank uses ten CGA5L1X7R2A475K160AC capacitors, with a conservative calculated effective estimate of 6.472 µF at the reviewed condition. The output uses two CGA6P3X7R1E226M250AB parts with a 19.448 µF conservative estimate, and GCM188R71H104KA57 is the selected bootstrap capacitor. Vendor-curve estimates are not production guarantees.

12

Provisional front-end protection

TPS48110AQDGXRQ1 controls two IAUTN15S6N025GATMA1 back-to-back MOSFETs, while WSLP1206R0250FEA provides the 25 mΩ current-sense element. The 5.0SMDJ60A-Q TVS remains candidate-only: its published clamp points do not by themselves prove a safe dynamic residual below the downstream converter limit.

Controller

TPS48110AQDGXRQ1 · provisional

Pass devices

2 × IAUTN15S6N025GATMA1 · SOA open

Current sense

WSLP1206R0250FEA · tolerance validation open

TVS candidate

5.0SMDJ60A-Q · not electrically locked

13

BOM maturity and evidence status

The locked HGS14F BOM contains exactly fifteen rows. Three rows are selected; twelve remain provisional because capacitance, dynamic protection, tolerance or exact low-power part-number evidence is still open. A candidate MPN does not promote a row beyond the maturity assigned by HGS14F.

14

Validation status and next evidence

Bench, thermal, EMI and compliance validation are all incomplete. Full front-end dynamic closure and full BOM release are also incomplete. Next evidence must lock the transient source, verify clamp and turn-off dynamics, demonstrate MOSFET SOA and energy margin, and measure electrical, fault, thermal and emissions behavior on the intended PCB and assembly.

• Lock voltage, duration, source impedance, repetition and reverse-event profiles.
• Validate TVS energy, MOSFET SOA, dynamic turn-off and parasitic overshoot.
• Measure regulation, ripple, startup, load steps, faults and inrush.
• Validate component and PCB temperature plus conducted and radiated EMI.
• Make compliance claims only after an authorized standard-specific test program.

15

Official sources and related engineering

Primary manufacturer documentation supports the selected identities and calculation inputs, while Hengshun's related application, solution, component and guide pages provide system context. Linked sources must be checked for revision and applicability before a project uses this candidate as an engineering input.